RATHNAKAR, EMBADI; PRADEEP KUMAR, DR.A. DESIGN AND FPGA IMPLEMENTATION OF A 128-BIT ASYNCHRONOUS GRAY CODE FIFO WITH ENHANCED ERROR MONITORING USING VERILOG HDL. International Journal of Technology, Leadership and Sciences, [S. l.], v. 2, n. 5, p. 123–135, 2026. Disponível em: https://ijtls.com/index.php/files/article/view/91. Acesso em: 3 oct. 2026.