E. RATHNAKAR and D. PRADEEP KUMAR, “DESIGN AND FPGA IMPLEMENTATION OF A 128-BIT ASYNCHRONOUS GRAY CODE FIFO WITH ENHANCED ERROR MONITORING USING VERILOG HDL”, IJTLS, vol. 2, no. 5, pp. 123–135, Sep. 2026, Accessed: Oct. 03, 2026. [Online]. Available: https://ijtls.com/index.php/files/article/view/91