RATHNAKAR E, PRADEEP KUMAR D. DESIGN AND FPGA IMPLEMENTATION OF A 128-BIT ASYNCHRONOUS GRAY CODE FIFO WITH ENHANCED ERROR MONITORING USING VERILOG HDL. IJTLS [Internet]. 2026 Sep. 30 [cited 2026 Oct. 3];2(5):123-35. Available from: https://ijtls.com/index.php/files/article/view/91