LOKESH, ATINARAPU; SILPA, DR.CHINNAIAHGARI. LOW-POWER FPGA IMPLEMENTATION OF SHA-256 USING CLOCK GATING AND PERFORMANCE MONITORING. International Journal of Technology, Leadership and Sciences, [S. l.], v. 2, n. 5, p. 250–261, 2026. Disponível em: https://ijtls.com/index.php/files/article/view/104. Acesso em: 5 oct. 2026.