LOW-POWER FPGA IMPLEMENTATION OF SHA-256 USING CLOCK GATING AND PERFORMANCE MONITORING
Keywords:
Xilinx Vivado, SHA-256, FPGA, Verilog HDL, Cryptographic Hash Function, Clock Gating, Cycle Counter, Low-Power Design, Embedded Systems, Hardware Security, Cryptographic Accelerator, IoT Security, Blockchain, Digital Signature, and Data Integrity.Abstract
The need for safe and energy-efficient cryptographic hardware has grown because to the quick development of digital communication, cloud computing, embedded systems, and the Internet of Things (IoT). One of the most popular cryptographic hash functions for guaranteeing data integrity, authentication, and secure communication is SHA-256 (Secure Hash Algorithm-256). A low-power FPGA implementation of SHA-256 using Verilog HDL is shown in this project, together with two extra hardware optimization modules: a Clock Gating Unit and a Performance Monitoring (Cycle Counter) Unit. By decreasing needless switching activity during idle periods by clock gating, the suggested architecture minimizes dynamic power consumption while maintaining the standard SHA-256 algorithm. Accurate performance evaluation and hardware verification are made possible by the integrated cycle counter, which keeps track of the total number of clock cycles needed to finish each hashing operation. Preprocessing, message scheduling, compression, hash generation, clock gating, and performance monitoring modules make up the design's modular architecture, which guarantees scalability, maintainability, and simplicity of integration into FPGA-based embedded systems. The Xilinx Vivado Design Suite is used to implement, simulate, synthesize, and validate the entire design. Without compromising the accuracy or compatibility of the conventional SHA-256 algorithm, experimental results show dependable hash creation, increased power efficiency, and improved execution monitoring. When low power consumption and hardware performance monitoring are crucial, the suggested design is appropriate for safe embedded programs, blockchain systems, digital signatures, IoT devices, cloud security, secure boot methods, and cryptographic accelerators. The design maintains excellent security, dependability, and operational efficiency while providing a workable and effective solution for contemporary FPGA-based cryptographic applications.
