IJTLS: Vol.2, Issue 5, September-October 2026

Articles

• ADVANCED ADAPTIVE CONTROL OF SOLAR-BATTERY MICROGRIDS USING NEURO-FUZZY INTELLIGENCE

  V TARUN NAYAK, T RAJESWARI (Author)

  1-10

  • FullArticle

  25 23

• WIRELESS CHARGING AND POWER MANAGEMENT SYSTEM FOR ELECTRIC VEHICLES USING DUAL INVERTER DRIVES

  SURAM NAVEEN, MR.S RADHA KRISHNA REDDY (Author)

  55-64

  • FullArticle

  26 26

• AUTOMATED DETECTION OF MALICIOUS URLS USING DEEP LEARNING

  KARUPATI SREE LAXMI, DR.P JOEL JOSEPHSON (Author)

  227-239

  • FullArticle

  18 22

• IMPLEMENT 32-BIT RISC-V ARCHITECTURE PROCESSOR USING VERILOG HDL

  KODAM SAI KRISHNA, DR.C LAXMIKANTH REDDY (Author)

  169-179

  • FullArticle

  18 34

• POWER QUALITY IMPROVEMENT IN HYBRID MICROGRIDS USING UNIFIED POWER QUALITY CONDITIONER

  NADIMINTI GOUTHAM, JYOTHIRMAI ANGULURI (Author)

  113-122

  • FullArticle

  28 21

• EFFICIENT RESIDENTIAL EV CHARGING USING PHOTOVOLTAIC ENERGY AND INTELLIGENT ENERGY SCHEDULING

  H SWARNALATHA, DR.P CHANDRASHEKHAR (Author)

  65-74

  • FullArticle

  29 27

• DESIGN AND FPGA IMPLEMENTATION OF AN INTELLIGENT AUTOMATIC BUS TICKETING SYSTEM WITH TRANSACTION CANCELLATION AND TIMEOUT RECOVERY USING FINITE STATE MACHINE

  Kammela Kavitha Rani, Dr.Jyothula Sunil Kumar (Author)

  240-249

  • FullArticle

  17 26

• OPTIMIZED SPEED CONTROL OF BLDC MOTORS USING WHALE OPTIMIZATION ALGORITHM-BASED PID CONTROLLER

  MANDA DEEPIKA, DR.G JAYA KRISHNA (Author)

  11-22

  • FullArticle

  34 28

• LOW-POWER FPGA IMPLEMENTATION OF A SINGLE-CYCLE QC-LDPC ENCODER USING CLOCK ENABLE AND BALANCED XOR TREE

  ANUSHA GAYINI, M NITHIN VARMA (Author)

  180-190

  • FullArticle

  18 23

• DESIGN AND FPGA IMPLEMENTATION OF A 128-BIT ASYNCHRONOUS GRAY CODE FIFO WITH ENHANCED ERROR MONITORING USING VERILOG HDL

  EMBADI RATHNAKAR, DR.A PRADEEP KUMAR (Author)

  123-135

  • FullArticle

  34 39

• INTELLIGENT UNIVERSAL ONBOARD CHARGER FOR ELECTRIC VEHICLES WITH SEAMLESS BUCK–BOOST TRANSITION

  KANCHARLA SUNITHA, MRS.T BHARGAVI (Author)

  75-84

  • FullArticle

  16 24

• LOW-POWER FPGA IMPLEMENTATION OF SHA-256 USING CLOCK GATING AND PERFORMANCE MONITORING

  ATINARAPU LOKESH, DR.CHINNAIAHGARI SILPA (Author)

  250-261

  • FullArticle

  13 15

• PERFORMANCE ENHANCEMENT OF ELECTRIC VEHICLE HYBRID ENERGY STORAGE SYSTEMS USING ULTRACAPACITORS AND BATTERY AGING ANALYSIS

  DOOSA NAVEEN, CH RAJA SRI (Author)

  23-32

  • FullArticle

  14 22

• DESIGN AND IMPLEMENTATION OF A LOW-POWER HYBRID ML-ACRA-KSA BASED 64-BIT ALU FOR AI AND DSP APPLICATIONS

  YERRAVALLI VAMSHIDHAR REDDY, MRS.RAPARTHI NAVYA (Author)

  191-203

  • FullArticle

  16 14

• A 27-1 LOW-POWER HALF-RATE 16-GBS CHARGE-MODE PRBS GENERATOR IN 1.2V, 65nm CMOS

  PEDDASAIGARI SRIPATHI, DR.G PRASANNA KUMAR (Author)

  136-140

  • FullArticle

  12 12

• SMART ENERGY MANAGEMENT OF HYBRID FUEL CELL –BATTERY STORAGE FOR RENEWABLE-POWERED EV CHARGING INFRASTRUCTURE

  CHENNAVENI ANILKUMAR, MR.M ROHIT (Author)

  85-92

  • FullArticle

  30 28

• THE "COUNTER-MAJORITARIAN DIFFICULTY" OF CLIMATE MODELS: JUDICIAL REVIEW AND EPISTEMIC AUTHORITY IN THE AGE OF THE ANTHROPOCENE

  TUTIKA SRINIVASA VISWANADH (Author)

  262-268

  • FullArticle

  16 16

• IMPROVED ON-BOARD CHARGING ARCHITECTURE WITH LOW DC-LINK CAPACITANCE FOR ELECTRIC VEHICLES

  G PRANEETH, THAMBADI NAVEEN KUMAR (Author)

  33-42

  • FullArticle

  25 33

• DESIGN AND IMPLEMENTATION OF AN FPGA-BASED INTELLIGENT MEDICAL ASSISTANT ROBOT WITH SAFETY CONTROLLER AND OPERATION COUNTER

  Cheruvukommu Kavya, Dr.T Srinivas Reddy (Author)

  204-217

  15 0

• A LIGHTWEIGHT CHALLENGE VALIDATION FRAMEWORK FOR ENHANCING STRONG PUF-BASED AUTHENTICATION IN IOT DEVICES

  MANISRI SANTRA, DR.N.V.K MAHALAKSHMI (Author)

  141-153

  • FullArticle

  19 26

• DESIGN AND IMPLEMENTATION OF A THREE-PHASE ISOLATED MULTILEVEL AC–DC CONVERTER FOR DUAL EV CHARGING

  GUMMADIDALA VINAY KUMAR, MR.M PAKKIRANNA (Author)

  93-102

  • FullArticle

  18 15

• SMART SOLAR ENERGY CONVERSION AND BATTERY CHARGING SYSTEM FOR ELECTRIC VEHICLE APPLICATIONS

  JARPULA RAMSINGH, RAMBABU YERRA (Author)

  43-54

  • FullArticle

  18 35

• AI-DRIVEN RTL GENERATION WITH ADAPTIVE ERROR CLASSIFICATION AND FUNCTIONAL VERIFICATION

  POLU VISHNU RAJ, JYOTHISRI VADLAMUDI (Author)

  218-226

  • FullArticle

  23 18

• DESIGN AND FPGA IMPLEMENTATION OF A HIGH-PERFORMANCE RISC-V EMBEDDED PROCESSOR USING KOGGE-STONE ADDER FOR LOW-LATENCY ARITHMETIC OPERATIONS

  KOPPISETTI SRI SAI KRISHNA KARTHIKEYA, Dr.E DEEPTHI (Author)

  154-168

  • FullArticle

  16 33

• INTELLIGENT RECONFIGURABLE CONVERTER FOR ENHANCED DUAL-BATTERY ELECTRIC VEHICLE PERFORMANCE

  KOPPULA RISHITHA, MRS.CH RAJA SRI (Author)

  103-112

  • FullArticle

  15 24