A LIGHTWEIGHT CHALLENGE VALIDATION FRAMEWORK FOR ENHANCING STRONG PUF-BASED AUTHENTICATION IN IOT DEVICES
Keywords:
Verilog HDL, FPGA, Xilinx Vivado, Internet of Things (IoT), Physical Unclonable Function (PUF), Strong PUF, Weak PUF, Challenge Validator, Hardware Authentication, Modeling Attack Resistance, Embedded Security, Device Authentication, Hardware Security, Cyber-Physical Systems.Abstract
Traditional software-based authentication can be vulnerable in resource-constrained systems such as those in IoT applications, where attacks such as physical tampering, key extraction, or computing power requirements can be a challenge. Physical Unclonable Functions (PUFs) have become one of the most promising physical security approaches in hardware due to the fact that manufacturing variations can generate unique and random responses to authenticate devices. Nevertheless, the traditional Strong PUF architectures are vulnerable to the modeling attack of unpredictable and invalid challenges. In this research, a Lightweight Challenge Validation Framework for Improving Robust PUF Based Authentication in IoT Devices is presented. The proposed architecture features lightweight Challenge Validator placed in front of the Strong Arbiter PUF to help ensure that the challenge vectors accepted and responded to are valid; on the other hand, invalid challenge vectors are filtered out before reaching the Strong Arbiter PUF to guarantee the generation of correct response vectors. The validated challenge is processed by the Strong PUF and Secure Registration and Reference Response are created by the Weak PUF. For the sake of reliably verifying the identity of the device, the architecture also comprises response comparison and authentication algorithms. The entire system is described in the Verilog Hardware Description Language (HDL) and simulated, synthesized and verified on FPGAs using the Xilinx Vivado Design Suite. Experimental results show that the proposed approach has minimal hardware costs, does not affect the system performance and improves the security against modeling attacks and authentication reliability. The modular design enables the integration of secure communication protocols, adaptive challenge generation, light-weight cryptographic modules and error correction algorithms in the future. The proposed framework is therefore a viable, scalable and FPGA-efficient solution for the hardware authentication problem for embedded systems, IOT, industrial automation, smart healthcare, automotive electronics and next generation cyber-physical systems.
