DESIGN AND FPGA IMPLEMENTATION OF AN INTELLIGENT AUTOMATIC BUS TICKETING SYSTEM WITH TRANSACTION CANCELLATION AND TIMEOUT RECOVERY USING FINITE STATE MACHINE

Authors

  • Kammela Kavitha Rani M.Tech, Department of Electronics and Communication Engineering, Malla Reddy Engineering College(Autonomous) Author
  • Dr.Jyothula Sunil Kumar Associate Professor,Department of Electronics and Communication Engineering, Malla Reddy(MR)deemed to be University. Author

Keywords:

FPGA, Verilog HDL, Finite State Machine (FSM), Xilinx Vivado, Fare Calculation, Transaction Cancellation, Timeout Recovery, Embedded Systems, Real-Time Processing, Smart Transportation, and Digital Ticketing.

Abstract

Manual ticketing or software-based systems are often used for traditional bus ticketing, and may be vulnerable to high-demand travel conditions, delays in transactions, duplicate tickets and inaccurate data. This study proposes the Design and FPGA Implementation of an Intelligent Automatic Bus Ticketing System with Transaction Cancellation and Timeout Recovery Using Finite State Machine (FSM) as a remedy to the above problems. The proposed system is developed in high speed hardware based ticket processing, more reliability and security by using Verilog Hardware Description Language (HDL) with Xilinx Vivado Design Suite. The architecture includes many functional modules, such as passenger input processing, destination selection, fare computation, payment verification, ticket production, transaction cancellation, timeout recovery, etc., and a centralized Finite State Machine (FSM) controller. The FSM manages all the system functions well and ensures that transactions are performed correctly and that data is transferred efficiently between hardware units. In addition, the cancel module allows for the safe termination of transactions as required and the timeout recovery module automatically detects a failed transaction and restores the system to a safe state. Results of functional simulation, RTL synthesis and implementation are used to validate the accuracy and stability of the proposed hardware architecture under various operating conditions. The suggested FPGA-based solution provides reduced processing latency, increased transaction dependability, effective hardware resource usage, and greater operational security when compared to traditional ticketing systems. The modular design also enables future integration with RFID and NFC payment systems, cloud-based ticket management systems, GPS-based transport monitoring systems, IoT-based smart transportation platforms and QR code-based verification of tickets. The proposed system is therefore a scalable, safe and energy efficient solution for next generation intelligent public transportation ticketing applications.

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Published

2026-09-30

How to Cite

Kavitha Rani, K., & Sunil Kumar, D. (2026). DESIGN AND FPGA IMPLEMENTATION OF AN INTELLIGENT AUTOMATIC BUS TICKETING SYSTEM WITH TRANSACTION CANCELLATION AND TIMEOUT RECOVERY USING FINITE STATE MACHINE. International Journal of Technology, Leadership and Sciences, 2(5), 240-249. https://ijtls.com/index.php/files/article/view/103