LOW-POWER FPGA IMPLEMENTATION OF A SINGLE-CYCLE QC-LDPC ENCODER USING CLOCK ENABLE AND BALANCED XOR TREE
Keywords:
FPGA, Verilog HDL, Clock Enable, Clock Gating, Balanced XOR Tree, Low Power Design, Error Correction Coding, Single Cycle Encoding, 5G Communication, Hardware Optimization, Wireless Communication, Digital Communication, QC-LDPC Encoder.Abstract
The wireless communication systems are gaining in popularity and in this regard, the need of low power consuming and good hardware performance based effective error correction techniques is increasing. Low-Density Parity-Check (LDPC) codes are an attractive option for use in modern communication systems like 5G, Wi-Fi, satellite communication and digital broadcasting, due to the excellent error correction ability of these codes, and their high throughput. The aim of this project is the implementation of a single cycle QC-LDPC Encoder in a FPGA, where two approaches for optimisation of the FPGA are used: Clock Enable (Clock Gating Concept) and Balanced XOR Tree. The proposed architecture achieves hardware efficiency, while keeping the same quasi-cyclic LDPC (QC-LDPC) encoding scheme and one-cycle operation while reducing the dynamic power consumption. The Clock Enable mechanism ensures that data is only captured into the input register when required during the allowed encoding sequence, thus avoiding the waste of clock switching and reducing power consumption during non-encoding clock cycles. Additionally, the Balanced XOR Tree rebalances the calculation of the parity without disturbing the parity bits generated, rebalancing by a hierarchical XOR implementation with minimum propagation time, minimum combinational logic depth and high temporal efficiency. All the architectures are designed, simulated, synthesized and implemented using Xilinx Vivado Design Suite. The experimental results show that the proposed power efficient encoder is using optimal logic, it provides high reliability of single cycle encoding performance, and the proposed encoder has the same throughput and encoding performance as the traditional QC-LDPC encoder. The suggested design can be applicable to FPGA based communication system such as 5G wireless system, Internet of Things (IoT) devices, satellite communication, Digital broadcasting and embedded system requiring functions with high speed, low power and error correction with hardware efficient way. The design is applicable and expandable for using in modern communication system using FPGA.
