IMPLEMENT 32-BIT RISC-V ARCHITECTURE PROCESSOR USING VERILOG HDL
Keywords:
RISC-V, RV32I Processor, Harvard Architecture, Verilog HDL, FPGA, Xilinx Vivado, Instruction Set Architecture (ISA), Arithmetic Logic Unit (ALU), Register File, Instruction Memory, Data Memory, Internet of Things Applications, and VLSI Design.Abstract
An open-source instruction set architecture (ISA) called RISC-V provides cost-effective processor development, flexibility and adaptability without any licensing restrictions. This project aims to design and implement a 32-bit RV32I RISC-V processor with Harvard Architecture using Verilog Hardware Description Language (HDL). This proposed architecture suggests separate instruction memory and data memory, enabling the concurrent fetch of instructions and data access, unlike the conventional architecture that has a shared memory for instructions and data. This independent memory configuration removes structural risks, reduces memory access conflicts, boosts the throughput of the execution and enhances processor performance. The processor architecture consists of several basic functional units such as the Program Counter (PC), Instruction Memory, Instruction Decode Unit, Register File, Arithmetic Logic Unit (ALU), Data Memory, and Write Back Unit. The processor has a basic instruction set, called RV32I, which includes arithmetic, logical, memory access, branch, and jump operations, all used in embedded and Internet of Things (IoT) applications. The entire design has been implemented using Verilog HDL and behavioral simulation, synthesis, and implementation verification is done using Xilinx Vivado Design Suite. Synthesis results demonstrate the efficient use of FPGA resources, hardware simplicity and memory layout, while the simulation results confirm that supported instructions are correctly executed. The modular design provides excellent scalability for future enhancements such as cache memory, interrupt management, multiplication and division extensions, peripheral interfaces, and integration of System-on-Chip (SoC). The proposed RV32I processor using Harvard architecture is an effective, reliable, and FPGA-friendly solution for applications like embedded systems, industrial automation, Internet of Things (IoT) devices, educational research, and next-generation digital computing.
