DESIGN AND FPGA IMPLEMENTATION OF A HIGH-PERFORMANCE RISC-V EMBEDDED PROCESSOR USING KOGGE-STONE ADDER FOR LOW-LATENCY ARITHMETIC OPERATIONS

Authors

  • KOPPISETTI SRI SAI KRISHNA KARTHIKEYA M.tech, Department of Electronics and Communication Engineering, Malla Reddy Engineering College. Author
  • Dr.E DEEPTHI Assistant Professor,Department of Electronics and Communication Engineering, Malla Reddy Engineering College. Author

Keywords:

Xilinx Vivado, RISC-V Processor, FPGA, Verilog HDL, Kogge-Stone Adder (KSA), Arithmetic Logic Unit (ALU), Multi-Cycle Processor, Low-Latency Computing, Parallel Prefix Adder, Hardware Acceleration, Digital System Design.

Abstract

Ripple carry and carry look-ahead adders are commonly used in the Arithmetic Logic Unit (ALU) of traditional RISC-V processors, significantly impacting processor speed and resulting in a substantial carry propagation delay during arithmetic calculations. In this work, we address these constraints with the design and FPGA implementation of a multi-cycle RISC-V Embedded Processor with high performance using the Kogge-Stone Adder for low latency arithmetic operations. The suggested processor is designed using the Verilog Hardware Description Language (HDL) and implemented with the Xilinx Vivado Design Suite. For reducing carry propagation delay and accelerating arithmetic calculation, a 32-bit Kogge-Stone Adder (KSA) is used in the ALU and Program Counter (PC). A multi-cycle control architecture coordinates the various parts of the processor, such as the Control Unit, Datapath Unit, Register File, ALU, Instruction Memory, Data Memory, Program Counter and Kogge-Stone Adder, to make sure they perform the instructions correctly. Behavioral simulation, RTL synthesis, timing analysis and implementation of the suggested hardware design are used to validate the accuracy and stability of the design for different instruction contexts. Experimental results indicate faster arithmetic processing, reduced processing delay, efficient usage of FPGA resources and lower on-chip power consumption when compared to the traditional RISC-V processor architectures. The design of the system can be scaled up and down for future improvements like pipelined execution, cache memory integration, floating-point arithmetic, AI accelerators, cryptographic extensions, and Internet of Things (IoT) embedded applications. Overall, the proposed FPGA-based RISC-V processor offers a high-speed, scalable, and power-efficient computing solution for modern embedded systems, real-time digital signal processing, edge computing, industrial automation, robotics, and beyond.

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Published

2026-09-30

How to Cite

SRI SAI KRISHNA KARTHIKEYA, K., & DEEPTHI, D. (2026). DESIGN AND FPGA IMPLEMENTATION OF A HIGH-PERFORMANCE RISC-V EMBEDDED PROCESSOR USING KOGGE-STONE ADDER FOR LOW-LATENCY ARITHMETIC OPERATIONS. International Journal of Technology, Leadership and Sciences, 2(5), 154-168. https://ijtls.com/index.php/files/article/view/94