DESIGN AND IMPLEMENTATION OF A LOW-POWER HYBRID ML-ACRA-KSA BASED 64-BIT ALU FOR AI AND DSP APPLICATIONS

Abstract

This work presents the design and FPGA implementation of an energy-efficient 64-bit hybrid ALU that utilizes a 64×64 Vedic Multiplier and a Hybrid Multi-Level Accuracy Configurable Radix-4 Adder (ML-ACRA) along with a Kogge-Stone Adder (KSA). The suggested design is designed to have better arithmetic performance and lower propagation latency due to parallel prefix computation capability of Kogge-Stone Adder and low power performance of ML-ACRA. By employing effective divide-and-conquer arithmetic strategies, the Vedic Multiplier further speeds up multiplication operations. All the hardware architecture is designed using a Hardware Description Language (HDL) known as Verilog and is implemented using the Xilinx Vivado Design Suite. Functional simulation, synthesis and implementation are used to establish the accuracy and dependability of the proposed design. Experimental results demonstrate that the obtained dynamic power, signal power, logic power and on-chip power reductions are significant when compared with conventional ALU architectures, while preserving high computational accuracy and throughput. The scalable integration and efficient utilization of FPGA resources through the modular architecture provide benefits to AI accelerators, DSP processors and high-performance embedded systems. The proposed hybrid ALU is an efficient architecture that balances speed, energy efficiency, and hardware complexity, making it suitable for use in next-generation intelligent computing platforms that require real-time arithmetic processing and energy-efficient hardware.