SAI KRISHNA, KODAM; LAXMIKANTH REDDY, DR.C. IMPLEMENT 32-BIT RISC-V ARCHITECTURE PROCESSOR USING VERILOG HDL. International Journal of Technology, Leadership and Sciences, [S. l.], v. 2, n. 5, p. 169–179, 2026. Disponível em: https://ijtls.com/index.php/files/article/view/95. Acesso em: 5 oct. 2026.