GAYINI, ANUSHA; NITHIN VARMA, M. LOW-POWER FPGA IMPLEMENTATION OF A SINGLE-CYCLE QC-LDPC ENCODER USING CLOCK ENABLE AND BALANCED XOR TREE. International Journal of Technology, Leadership and Sciences, [S. l.], v. 2, n. 5, p. 180–190, 2026. Disponível em: https://ijtls.com/index.php/files/article/view/96. Acesso em: 5 oct. 2026.