[1]
A. LOKESH and D. SILPA, “LOW-POWER FPGA IMPLEMENTATION OF SHA-256 USING CLOCK GATING AND PERFORMANCE MONITORING”, IJTLS, vol. 2, no. 5, pp. 250–261, Sep. 2026, Accessed: Oct. 05, 2026. [Online]. Available: https://ijtls.com/index.php/files/article/view/104