LOKESH, ATINARAPU, and DR.CHINNAIAHGARI SILPA. “LOW-POWER FPGA IMPLEMENTATION OF SHA-256 USING CLOCK GATING AND PERFORMANCE MONITORING”. International Journal of Technology, Leadership and Sciences 2, no. 5 (September 30, 2026): 250–261. Accessed October 5, 2026. https://ijtls.com/index.php/files/article/view/104.